The ability of personal computers (PCs) to use video has grown dramatically in recent years. The advent of telecommuting and real time video conferencing has greatly expanded the applications used to capture and display digital video (DV) data in a personal computer system.
A representative personal computer (PC) system suitable for the capture and display of DV data is shown in FIG. 1. In general, the personal computer 100 includes a bus 102 used for communicating information, a host processor 104 coupled with the bus 102 for processing information and instructions, a computer main memory unit 106 (e.g., random access memory unit) coupled to the bus 102 by way of a bus controller 110 used to arbitrate access to the main memory unit 106. The bus controller 110 includes a first in first out (FIFO) buffer 112 used to queue data waiting to be stored in the main memory unit 106. The personal computer 100 also includes a data storage device 114 such as a magnetic or optical disk and/or disk drive capable of storing information and instructions. Such information includes digital video (DV) data. The data storage device 114 is coupled to the bus 102 by way of a data storage host controller 116 used to mediate access of the data storage device 114 to the bus 102. The data storage host controller 116 also includes a data storage host FIFO buffer 115 used to queue in-transit data. The personal computer 100 also includes an isochronous DV data unit 118 coupled to the bus 102 by way of a DV host controller 120 used to mediate access of the DV data unit 118 to the bus 102. The DV host controller 118 includes a FIFO buffer 119 capable of queuing DV data waiting to be transmitted during the correct channel time slot. DV data may be transmitted over a serial bus 121 using any type of transmission protocol. One example of such a transmission protocol for the serial bus 121, which may be used to transmit DV data, is referred to as the IEEE standard 1394. Other transmission protocols, such as those used by Sony or Panasonic, may also be used to transmit DV data. The DV host controller 120 generally receives and transmits isochronous data such as DV data over the serial bus 121.
The personal computer 100 also includes a display monitor 122 coupled to the bus 102. The display monitor 122 is suitable for generating a display from display information supplied by a graphics hardware card 124 coupled to the bus 102. The graphics hardware card 124 contains a display processor 126 which executes a series of display instructions found within a display list. The host processor 104 or display processor 126 supplies data and control signals to a frame buffer which refreshes the display device 122 for rendering images on the display device 122.
In order to display DV data stored in the data storage device 114, for example, the data storage host controller 116 retrieves the appropriate DV data from the data storage device 114 and, if necessary, queues it in the data storage host controller FIFO buffer 115. Under control of the system processor 104, the data storage host controller 116 sends the DV data to the bus 102 to be "written" to a data buffer 127 located in the system main memory device 106 under control of the bus controller 110. The DV data stored in the data buffer 127 is then passed to the DV data host controller 120 by way of the bus 102 under the control of the bus controller 110. The DV data is queued in the DV data host FIFO buffer 119 until an appropriate time channel is available, at which time the DV data is passed to the DV data unit 118 by way of the serial bus 121.
Unfortunately, current PC operating systems such as Win95.TM. and System 7.TM. are not real-time operating systems. Typically, data from the data storage device 114 is requested in large blocks and is referred to as being asynchronous in nature. By asynchronous in nature it is meant that there is no temporal relationship with the delivery of data, and consequently, data may arrive in large blocks. The most serious bottleneck in the transfer of DV data occurs when the FIFO buffer 112 included in the bus controller 110 transfers large blocks of data to the main system memory device 106. This "flushing" of data from the FIFO buffer 112 interrupts the flow of DV data since the bus 102 is no longer accessible. This interruption in the transfer of the DV data causes the DV controller 120 to "miss" time slots or time channels critical for the proper capture and/or display of the DV data. In a typical isochronous DV data transfer, any DV data packet must be available at regular intervals having a period of, for example, 125 .mu.s.
However, the bus controller 110 generally follows arbitration algorithms which give devices such as the data storage host controller 116 priority access to the bus 102. In this manner, devices writing data to the system main memory 106 by way of bus 102 as controlled by the bus controller 110 make the bus 102 inaccessible to other devices for long periods of time. By way of example, if a large block of data is being transferred to the system main memory device 106, the bus controller 110 must temporarily store the large block of data in the FIFO buffer 112 due to long write cycle times associated with the system main memory device 106. The large block of data stored in the FIFO buffer 112 must then be transferred, or "flushed", to the system main memory 106 over a period of time which may be substantially longer than the time slot or time channel available for DV data transfer.
Unfortunately, any additional write requests from any device to the system main memory device 106 are typically given priority over any read request by the bus controller 10 since reads are "blocked" until the write FIFO buffer is "flushed". The prioritization of the additional write requests further increases the time the DV data controller 120 cannot read DV data from the system main memory device 106. This "starving" of the device requesting DV data from the system main memory device 106 often causes the DV data controller 120 to have insufficient data for the next isochronous time channel. This lack of data causes the DV data controller to "miss" a time channel resulting in potential frame data loss or frame synchronization problems.
Therefore, a method and an apparatus for guaranteeing the bandwidth of an isochronous data transfer in a personal computer system is needed.